This is my Masters thesis topic. In previous work by our research group, a microprocessor cache extension was developed that was capable of both increasing cache access speed while reducing power consumption. This exention relies on the fact that a directly-mapped cache uses both less power and operates more quickly than a set-associate cache. By storing set information from previous memory transactions, it is possible to access access a set-associative cache in a directly-mapped fashion. A more detailed account of the operation of a Location Cache can be read in a previous work by Bin Qi, found here.
With both Intel and AMD aggressively pursuing chip multiprocessors (CMP), commonly called multi-core systems, there could be great benefit in expanding this theory to support such processors. My work involves adapting the location cache concept to support CMP systems. Limitations of the Simplescalar simulator used in our previous work required us to switch to the more powerful Virtutech Simics simulator. While Simics is a commercial simulator, they graciously provide academic licensing free of charge. I have created a new model of the Location Cache system from scratch to work with Simics' included generic cache system (g-cache). From here I am working on perfecting the use of the Location Caches in CMP systems, including the timing and coherency issues such a setup introduces.
I have completed the majority of implementation and testing, and should begin writing my thesis in the next few months. I am currently on track to finish the project in time for an official graduation in March 2008.
